1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and, more particularly, to an LCD device capable of easily controlling a sequence of a driving voltage and a reset signal supplied to a timing controller and easily removing an induced voltage, which is to be applied to the timing controller, applied to a reset circuit.
2. Description of the Related Art
In general, the application coverage of a liquid crystal display (LCD) extends because of its characteristics that it is lighter, thinner, and driven at a low power consumption. Thus, the LCD is commonly used as a means for displaying images in mobile computers, mobile phones, office automation equipment, or the like.
The LCD displays a desired image on its screen by controlling the amount of transmission of light according to a video signal applied to a plurality of control switching elements arranged in a matrix form.
The LCD includes a liquid crystal panel including a color filter substrate, an upper substrate, and a thin film transistor (TFT) substrate, a lower substrate, which face, between which and a liquid crystal layer is formed, and a driver that supplies a scan signal and image information to the liquid crystal panel to operate the liquid crystal panel.
The related art LCD will now be described with reference to the accompanying drawings.
As shown in FIG. 1, the related art LCD includes a liquid crystal panel including a thin film transistor (TFT) array substrate 1 with gate lines GL1˜GLn and data lines DL1˜DLn crossing to define a plurality of pixels, and a driving unit for driving the liquid crystal panel.
The driving unit includes a timing controller 2, a gate driver 4, a data driver 3, and a driving voltage generating unit 7.
The timing controller 2 generates a gate control signal and a data control signal for driving each pixel by using signals inputted from a system 6, realigns pixel data from the system 6, and outputs the same.
The gate driver 4 drives the gate lines GL1˜GLn by using the gate control signal supplied from the timing controller 2, and the data driver 3 supplies pixel data to the corresponding data lines DL1˜DLm according to the data control signal supplied from the timing controller 2.
Although not shown, the driving voltage generating unit 7 includes a boosting unit (not shown) for converting input power VIN supplied from the system 6 into a certain level of input voltage VIN′ (e.g., 3V to 5V) and outputting the same; and a DC/DC converter (not shown) for generating various types of voltages to be used at the timing controller 2, the gate driver 4, and the data driver 3 by using the input voltage VIN′ from the boosting unit. Here, the input power VIN is obtained by converting an AC voltage of 110V or 220V supplied to the system from the exterior into a certain level of DC voltage through an AC/DC converter (not shown). Generally, the input power VIN has a level of 12V.
With reference to FIG. 1, the general LCD includes a reset signal generating unit 5 that generates a reset signal VRST for initializing a circuit operation at an early stage of operation, and supplies it to the timing controller 2.
FIG. 2 shows a detailed circuit diagram of the reset signal generating unit 5. As shown in FIG. 2, the reset signal generating unit 5 includes a transistor Q including an emitter connected to a driving voltage VCC input terminal to constitute a first node n1, a base constituting a second node n2, and a collector constituting a third node n3; a first resistor R1 connected between the first node n1 and the second node n2, a second resistor R2 connected between the second node n2 and a ground, a third resistor R3 connected between the third node n3 and the ground, and a fourth resistor R4 connected between the third node n3 and the reset signal (VRST) output terminal; and a capacitor C1 connected between the reset (VRST) output terminal and the ground. Here, the voltage supplied from the DC/DC converter (not shown) of the driving voltage generating unit 7 to the driving voltage (VCC) input terminal is the same as the driving voltage VCC supplied from the DC/DC converter to the timing controller 2.
The driving of the reset signal generating unit 5 having such circuit configuration will now be described.
First, when the input power VIN, basic power, for driving the entire LCD is applied to the driving voltage generating unit 7, the input power VIN is converted into the input voltage VIN′ by the boosting unit (not shown) of the driving voltage generating unit 7, and the input voltage VIN′ is converted into the driving voltage VCC by the DC/DC converter (not shown) of the driving voltage generating unit 7 and outputted. The driving voltage VCC is supplied to the timing controller 2 and, at the same time, applied to the driving voltage VCC input terminal of the reset signal generating unit 5. Here, the driving voltage VCC is generally 3.3V.
Accordingly, the voltage of the second node n2 has a level previously designed by a voltage distribution rule according to a ratio of the resistance value of the first resistor R1 and that of the second resistor R2, and the transistor Q is turned on by the voltage of the second node n2.
Thus, the voltage of the third node n3 has the same level as the driving voltage VCC of the driving voltage (VCC) input terminal, and the reset signal VRST is outputted via the reset signal VRST output terminal after an RC delay by the fourth resistor R4 and the capacitor C1.
Namely, the reset signal generating unit 5 generating the reset VRST signal upon simultaneously receiving the driving voltage VCC supplied from the DC/DC converter (not shown) of the driving voltage generating unit 7 to the timing controller 2. In this case, however, the sequence of the reset signal VRST is sufficiently behind the driving voltage VCC due to the RC delay by the fourth resistor R4 and the capacitor C1. Thus, the timing controller 2 receives the reset signal VRST after the driving voltage VCC is applied from the DC/DC converter (not shown) of the driving voltage generating unit 7, so the elements within the timing controller 2 are initialized.
However, the reset signal generating unit 5 is designed to have a sufficiently high RC delay due to the fourth resistor R4 and the capacitor C1 in order to make the reset signal VRST to be sufficiently behind in sequence than the driving voltage VCC. At this time, however, a voltage level rising time of the reset signal VRST is lengthened, so the internal elements of the timing controller 2 cannot recognize the reset signal VRST from the reset signal generating unit 5 as a signal for initialization. Namely, the timing controller 2 is not initialized.
Also, in the related art general LCD, the induced voltage applied to the timing controller 2 is applied to the reset signal (VRST) output terminal of the reset signal generating unit 5, there is no path for removing the induced voltage.
In addition, in the related art general LCD, the transistor Q, namely, the bipolar junction transistor (BJT), a major element of the reset signal generating unit 5 has much deviation over temperature, so there is a high possibility that an error occurs in generating the reset signal (VRST).